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| the information in this document is subject to change without notice. mos integrated circuit m m m m pd98409 atm light sar controller 1997, 1998 ? document no. s12775ej2v0ds00 (2nd edition) date published may 1998 n cp(k) printed in japan data sheet the mark shows major revised points. description the m pd98409 (neascot-s40c tm ) is a high-performance sar chip for segmentation and reassembly of atm cells. provided with a pci (peripheral component interconnect) bus interface control memory and supporting a mpeg packet transfer engine function to mitigate the workload of the cpu in transferring compressed image data, this chip has ideal specifications for use in a set top box (stb) to interface with an atm network. the m pd98409 conforms to atm forum recommendations and has aal5-sar sublayer and atm layer functions. features ? conforms to atm forum ? pci bus interface (5/3.3 v, 32/64 bits, 33 mhz) conforms to pci local bus specification revision 2.1 ? aal-5 sar sublayer and atm layer functions ? hardware support of aal-5 processing (non-aal-5 processing can be supported in software) ? supports up to 64 virtual channels (vc) (64-vc control memory) ? two traffic shapers for transmission scheduling ? mpeg packet transfer engine mitigating the workload of compressed image data transfer by cpu ? receive fifo of 12 cells ? phy device i/f: utopia level-1 interface (octet/cell level handshake) ? jtag boundary scan test functions ? 0.35- m m cmos process, +5/+3.3-v power supply - bus interface +5 v : +5/+3.3-v power supply - bus interface +3.3 v : +3.3-v single power supply ordering information part number package m pd98409gn-lmu 240-pin plastic qfp (0.5-mm fine pitch) (32 32 mm)
2 m m m m pd98409 example of system configuration m pd98409 cpu memory atm stb pci bus line interface mpeg decoder block block diagram pci interface dma controller receive phy interface rx utopia interface phy control interface tx utopia interface transmit phy interface control memory (64 vcs) control memory interface mpeg packet transfer engine pci interface block receive data fifo (12 cells) transmit data fifo (2 cells) transmit controller sequencer receive controller 3 m m m m pd98409 pin configuration (top view) ? 240-pin plastic qfp (0.5-mm fine pitch) (32 32 mm) gnd gnd 60 1 gnd 2 ad29 3 ad28 4 ad27 5 ad26 6 gnd 7 vdd5 8 ad25 9 ad24 10 pcbe3_b 11 gnd 12 idsel 13 vdd5 14 gnd 15 ad23 16 ad22 17 ad21 18 ad20 19 gnd 20 vdd3 21 ad19 22 ad18 23 ad17 24 ad16 25 gnd 26 pcbe2_b 27 frame_b 28 irdy_b 29 trdy_b 30 gnd 31 vdd5 32 devsel_b 33 stop_b 34 perr_b 35 gnd 36 serr_b 37 par 38 pcbe1_b 39 vdd3 40 gnd 41 ad15 42 ad14 43 ad13 44 ad12 45 gnd 46 vdd5 47 ad11 48 ad10 49 ad9 50 ad8 51 vdd5 52 gnd 53 pcbe0_b 54 ad7 55 ad6 56 ad5 57 vdd5 58 gnd 59 vdd3 vdd3 120 61 ad4 62 ad3 63 ad2 64 ad1 65 gnd 66 vdd5 67 ad0 68 req_b 69 gnd 70 gnt_b 71 gnd 72 busclk 73 gnd 74 intr_b 75 vdd5 76 gnd 77 gnd 78 e2pclk 79 gnd 80 vdd3 81 e2pdo 82 e2pdi 83 e2pcs 84 gnd 85 ic 86 ic 87 ic 88 ic 89 gnd 90 vdd3 91 ic 92 ic 93 ic 94 ic 95 gnd 96 ic 97 gnd 98 ic 99 vdd3 100 gnd 101 ic 102 ic 103 ic 104 ic 105 ic 106 ic 107 ic 108 ic 109 gnd 110 ic 111 gnd 112 ic 113 ic 114 ic 115 rx7 116 rx6 117 rx5 118 rx4 119 gnd gnd 121 180 gnd 179 ca8 178 ca7 177 ca6 176 ca5 175 gnd 174 ca4 173 ca3 172 ca2 171 ca1 170 vdd3 169 gnd 168 ca0 167 phce_b 166 phoe_b 165 cd0 164 cd1 163 cd2 162 gnd 161 vdd3 160 cd3 159 cd4 158 cd5 157 gnd 156 cd6 155 cd7 154 phrw_b 153 phint_b 152 vdd3 151 gnd 150 tx0 149 tx1 148 tx2 147 tx3 146 gnd 145 tx4 144 tx5 143 tx6 142 tx7 141 vdd3 140 gnd 139 tclk 138 gnd 137 tenbl_b 136 tsoc 135 full_b/txclav 134 rsoc 133 renbl_b 132 empty_b/rxclav 131 vdd3 130 gnd 129 rclk 128 gnd 127 rx0 126 rx1 125 rx2 124 rx3 123 gnd 122 vdd3 vdd3 181 240 ad30 239 ad31 238 vdd5 237 gnd 236 rst_b 235 vdd5 234 gnd 233 rstout_b 232 ic 231 ic 230 ic 229 gnd 228 ic 227 ic 226 physel1 225 ic 224 gnd 223 nc 222 gnd 221 vdd3 220 jrst_b 219 jms 218 jdo 217 jdi 216 gnd 215 jck 214 gnd 213 ic 212 ic 211 ic 210 ic 209 ic 208 gnd 207 vdd3 206 ic 205 ic 204 ic 203 ic 202 vdd3 201 gnd 200 ic 199 l 198 l 197 gnd 196 po0 195 po1 194 po2 193 po3 192 gnd 191 vdd3 190 lastb 189 la0 188 la1 187 gnd 186 la2 185 la3 184 la4 183 la5 182 pd98409gn-lmu m nc : no connection. leave this pin open. ic : input pin with pull-down resistor for internal test. it is recommended to fix this pin to the low level. l : fix this pin to the low level. 4 m m m m pd98409 pin names ad31_ad0 : address/data phint_b : phy interrupt busclk : bus clock phoe_b : phy output enable ca8-ca0 : phy device address phrw_b : phy read/write cd7-cd0 : phy device data physel1 : phy select devsel_b : device select po3-po0 : generic output port e2pclk : clock for eeprom tm rclk : receive clock e2pcs : eeprom chip select renbl_b : receive enable e2pdi : serial data input from eeprom req_b : request e2pdo : serial data output to eeprom rsoc : receive start of cell empty_b/rxclav: phy empty / rx cell available rst_b : reset frame_b : cycle frame rstout_b : reset output full_b/txclav : phy buffer full / tx cell available rx7-rx0 : receive data bus gnd : ground serr_b : system error gnt_b : grant stop_b : stop idsel : id select tclk : transmit clock intr_b : interrupt tenbl_b : transmit enable irdy_b : initiator ready trdy_b : target r eady jck : jtag test pin tsoc : transmit start of cell jdi : jtag test pin tx7-tx0 : transmit data bus jdo : jtag test pin v dd3 : +3.3 v power supply jms : jtag test pin v dd5 : +5 v power supply jrst_b : jtag test pin la5-la0 : internal test pin lastb : internal test pin par : parity pcbe_b3-pcbe_b0: bus command and byte enables perr_b : parity error phce_b : phy chip enable 5 m m m m pd98409 contents 1. pin function ............................................................................................................. ......................... 6 1.1 phy device interface pin................................................................................................. .............................. 6 1.1.1 utopia interface....................................................................................................... .......................... 6 1.1.2 phy device control interface ........................................................................................... .................. 7 1.2 bus interface pins....................................................................................................... ................................... 8 1.3 serial eeprom interface pins ............................................................................................. ....................... 10 1.4 jtag boundary scan pins.................................................................................................. ........................ 10 1.5 other pins............................................................................................................... ...................................... 11 1.6 power and ground pins .................................................................................................... .......................... 11 2. electrical specifications ................................................................................................ ........ 12 3. package drawing .......................................................................................................... ............... 33 4. soldering conditions ..................................................................................................... ............ 34 6 m m m m pd98409 1. pin function the pin function of the m pd98409 is descibed below. a detailed explanation of how to use each pin, and the points to be noted in using the pins are given in m pd98409 users manual (document number: s12776e). be sure to refer to this users manual. the following describes the i/o levels in the tables. lv-ttl input : can be connected to 5 v cmos output ttl output : can be connected to 5 v ttl input, v oh = 3.3 v, i ol = 6 ma cmos output : 3.3 v cmos output, v oh = 3.3 v, i ol = 12 ma pci input : 5/3.3 v pci input pci output : 5/3.3 v pci output 1.1 phy device interface pin phy device interfaces include a utopia interface through which the m pd98409 transfers atm cells with a phy device, and a phy control interface by which the m pd98409 controls the phy device. 1.1.1 utopia interface (1/2) pin name pin no. i/o i/o level function rx7-rx0 116 - 119, 123 - 126 i lv-ttl receive data bus. rx7 through rx0 constitute an 8-bit input bus which inputs data received from a network in byte format from a phy device. the m pd98409 loads data in at the rising edge of rclk. rsoc 133 i lv-ttl receive start cell. the rsoc signal is input in synchronization with the first byte of the cell data from a phy device. this signal remains high while the first byte of the header is input to rx7 through rx0. renbl_b 132 o ttl receive enable. the renbl_b signal indicates to a phy device that the m pd98409 is ready to receive data in the next clock cycle. empty_b/ rxclav 131 i lv-ttl phy output buffer empty/rx cell available. this signal notifies the m pd98409 that there is no cell data to be transferred in the receive fifo and that no receive data can be supplied to the phy device. when the utopia interface is in the octet-level handshake mode, this signal serves as empty_b, indicating that the data on rx7 through rx0 are invalid in the current clock cycle. in the cell-level handshake mode, it serves as rxclav, indicating that there is no cell to be supplied next after the transfer of the current cell is completed. rclk 128 o ttl receive clock. this is a synchronization clock used to transfer cell data with the phy device at the receive side. the system clock input to the busclk pin is output from this pin as is. tx7-tx0 141 - 144, 146 - 149 o ttl transmit data bus. tx7 through tx0 constitute an 8-bit output bus which outputs transmit data in byte format to a phy device. the m pd98409 outputs data at the rising edge of tclk. tsoc 135 o ttl transmit start of cell. the tsoc signal is output in synchronization with the first byte of transmit cell data. 7 m m m m pd98409 (2/2) pin name pin no. i/o i/o level function tenbl_b 136 o ttl transmit enable. the tenbl_b signal indicates to a phy device that data has been output to tx7 through tx0 in the current clock cycle. full_b/ txclav 134 i lv-ttl phy buffer full/tx cell available. this signal notifies the m pd98409 that the input buffer of the phy device is full and that the device can receive no more data. when the utopia interface is in the octet-level handshake mode, the phy device inputs an inactive level to receive cell data. in the cell- level handshake mode, the phy device inputs a signal that indicates that the phy device can receive all the next one cell of data after the current cell has been completely transferred. tclk 138 o ttl transmit clock. this is a synchronization clock used to transfer cell data with the phy device at the transmission side. the system clock input to the busclk pin is output from this pin as is. 1.1.2 phy device control interface pin name pin no. i/o i/o level function phrw_b 153 o ttl phy read/write. the m pd98409 indicates the direction in which the phy device is controlled, by using phrw_b. 1: read 0: write phoe_b 165 o ttl phy output enable. the m pd98409 enables output from the phy device by making phoe_b low phce_b 166 o ttl phy chip enable. the m pd98409 makes phce_b low to access a phy device. phint_b 152 i lv-ttl phy interrupt. this is an interrupt input signal from a phy device. the phy device indicates to the m pd98409 that it has an interrupt source, by inputting a low level to phint_b. rstout_b 232 o ttl reset output. this is a signal to reset a phy device. the m pd98409 makes this pin low for the duration of 11 to 22 clock cycles when a low level is input to the rst_b pin or a software reset is executed. cd7-cd0 154, 155, 157 - 159, 162 - 164 i/o 3-state lv-ttl in ttl out phy device data. cd7 through cd0 constitute an 8-bit data bus. these pins are three- state i/o pins. they are used to transfer data with a phy device. ca8-ca0 178 - 175, 173 - 170, 167 o ttl phy device address. ca8 through ca0 constitute a 9-bit address bus that outputs an address to a phy device during read/write operation. 8 m m m m pd98409 1.2 bus interface pins the m pd98409 employs a 32-bit pci bus interface as a bus interface with the host. this interface conforms to pci local bus specification revision 2.1. (1/2) pin name pin no. i/o i/o level function ad31-ad0 238, 239, 3 - 6, 9, 10, 16 - 19, 22 - 25, 42 - 45, 48 - 51, 55 - 57, 62 - 65, 68 i/o 3-state pci address/data. ad31 through ad0 are 32 bits of multiplexed address and data bus signals. when the m pd98409 operates as the bus master, it drives an address at the first one clock, and transfers data at the second clock and onward. pcbe3_b pcbe2_b pcbe1_b pcbe0_b 11, 27, 39, 54 i/o 3-state pci bus command and byte enable. these signals define bus commands (generated bus transaction) in an address phase. in a data phase, they indicate which byte lane holds valid data. the pcbe3_b pin corresponds to byte 3 (bits 31 through 24), and pcbe0_b pin corresponds to byte 0 (bits 7 through 0). par 38 i/o 3-state pci parity. this signal inputs/outputs an even parity on the ad31 through ad0 and pcbe3_b through pcbe0_b pins including the par signal. when the m pd98409 operates as the master, the par signal is output in the address and write data phases. when the m pd98409 operates as a target, the par signal is output in the read data phase. frame_b 28 i/o sustained 3-state pci frame. this signal indicates the start and period of bus transaction. when this signal becomes active, it indicates the start of bus transaction. while it is active, data is transferred. when the next data transfer phase is for the last data of the transaction, this signal becomes inactive. trdy_b 30 i/o sustained 3-state pci target ready. this signal goes low when the target device is ready to complete the transaction of the current data phase. this signal is used in pairs with irdy_b. when both irdy_b and trdy_b are low, read/write data transfer is executed. irdy_b 29 i/o sustained 3-state pci initiator ready. this signal goes low when the initiator is ready to complete the transaction of the current data phase. this signal is used in pairs with trdy_b. when both irdy_b and trdy_b are low, read/write data transfer is executed. if both frame_b and irdy_b are inactive, the bus cycle is not executed, and wait cycles are inserted until both irdy_b and trdy_b become active. 9 m m m m pd98409 (2/2) pin name pin no. i/o i/o level function stop_b 34 i/o sustained 3-state pci stop. this signal goes low when the target device requests the master device to stop the current transaction. devsel_b 33 i/o sustained 3-state pci device select. this signal goes low when the m pd98409 operates as a target and recognizes an address after the frame_b signal has become active. when the m pd98409 operates as the master, it samples this signal to check to see whether a target device has been selected. idsel 13 i pci initialization device select. this signal inputs a high level when the configuration register of the m pd98409 is read/written. req_b 69 o note pci request. the m pd98409 requests the arbiter for the bus mastership by making this signal low. gnt_b 71 i pci grant. this signal goes low when the arbiter grants the m pd98409 the bus mastership. perr_b 35 i/o sustained 3-state pci parity error. this signal indicates that the m pd98409 has detected a parity error. it is enabled when the parity error response bit of the configuration register is set to 1. serr_b 37 o n-ch open-drain system error. this signal indicates that the m pd98409 has detected an address parity error. it is enabled when both the parity error response and system error enable bits of the configuration register are set to 1. intr_b 75 o n-ch open-drain interrupt output. pull up this pin because it outputs an open-drain signal. intr_b informs the cpu that the interrupt bit (not masked) of the gsr register is set. busclk 73 i pci pci bus clock. bus clock input pin. it inputs a clock of up to 33 mhz. rst_b 235 i pci reset. the rst_b signal initializes the m pd98409 (on starting). when a low level is input to rst_b, the internal state machine and registers of the m pd98409 are reset, and all the 3-state signals go into a high- impedance state. when this signal is input while the m pd98409 is operating, the operating status at that time is lost. keep the input to rst_b low at least for the duration of 1 clock cycle. do not access the m pd98409 at least for 20 clocks after it has been reset. note although the pci local bus specification revision 2.1 specifies that the req_b pin go into a high- impedance state while a low level is input to the rst_b pin, the req_b pin of the m pd98409 outputs a high level. 10 m m m m pd98409 1.3 serial eeprom interface pins the m pd98409 has an interface for serial eeprom supporting the microwire tm interface. some of the contents of the pci configuration register can be loaded from the eeprom connected. as the eeprom, nm93c46l of national semiconductor corp. is recommended. pin name pin no. i/o i/o level function e2pcs 84 o ttl eeprom chip select. a chip select signal for eeprom. leave this pin open when it is not used. e2pdi 83 i ttl internally pulled up eeprom data input. this pin is connected to the data output pin of the eeprom. pull up or open this pin when it is not used. e2pdo 82 o ttl eeprom data output. this pin is connected to the data input pin of the eeprom. pull up or open this pin when it is not used. e2pclk 79 o ttl eeprom clock. this pin supplies a clock necessary for data transfer with the eeprom. it outputs the clock input to the busclk pin divided by 36. leave this pin open when it is not used. 1.4 jtag boundary scan pins (these functions can be supported by request.) pin name pin no. i/o i/o level function jdi 216 i lv-ttl jtag test data input. the jdi pin is used to input data to the jtag boundary scan circuit register. normally, fix this pin to high or low level. jdo 217 o 3-state ttl jtag test data output. the jdo pin is used to output data from the jtag boundary scan circuit register. it changes output at the falling edge of the clock input to the jck pin. normally, leave this pin open. jck 214 i lv-ttl jtag test clock. this pin is used to supply a clock to the jtag boundary scan circuit register. normally, fix this pin to a high or low level. jms 218 i lv-ttl jtag test mode select. normally, fix this pin to a high or low level. jrst_b 219 i lv-ttl jtag test reset. this pin initializes the jtag boundary scan circuit register. normally, fix this pin to a low level. 11 m m m m pd98409 1.5 other pins pin name pin no. i/o i/o level function physel1 225 i lv-ttl internal test pin. input a low level to this pin. po3-po0 192 - 195 o cmos general-purpose output port. general-purpose output port pins. these pins output the value written to the gpor register. la5-la0 182 - 185, 187, 188 o ttl internal test pins. leave these pins open during normal operation. lastb 189 o ttl internal test pin. leave this pin open during normal operation. 1.6 power and ground pins pin name pin no. i/o function v dd3 21, 40, 61, 81, 91, 100, 120, 130, 140, 151, 160, 169, 181, 190, 201, 206, 220, 240 ? +3.3-v power supply. these pins supply +3.3 v to the chip. v dd5 8, 14, 32, 47, 52, 58, 67, 76, 234, 237 ? +5 v power supply. these pins supply +5 v to the chip when a +5-v bus interface is used. supply +3.3 v to these pins when a +3.3-v bus interface is used. gnd 1, 2, 7, 12, 15, 20, 26, 31, 36, 41, 46, 53, 59, 60, 66, 70, 72, 74, 77, 78, 80, 85, 90, 96, 98, 101, 110, 112, 121, 122, 127, 129, 137, 139, 145, 150, 156, 161, 168, 174, 179, 180, 186, 191, 196, 200, 207, 213, 215, 221, 223, 228, 233, 236 ? ground. connect to ground. 12 m m m m pd98409 2. electrical specifications absolute maximum ratings parameter symbol conditions ratings unit supply voltage v dd3 - 0.5 to +4.6 v v dd5 note v dd3 v dd5 - 0.5 to +6.6 v input voltage v i except pin pci, v i < v dd3 + 3.0 v - 0.5 to +6.6 v pci pin C5.5 to +11.0 v output voltage v o except pci pin and po0-po3, v o < v dd3 + 3.0 v - 0.5 to +6.6 v po3-po0, v o < v dd3 + 0.5 v - 0.5 to +4.6 v pci pin C0.5 to +6.6 v output current i o except pci pin and po0-po3 20 ma po3-po0 40 ma pci pin 20 ma operating ambient temperature t a 0 to +70 c storage temperature t stg - 65 to +150 c note v dd5 : dedicated power supply for clamping diode caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). be sure to use the product(s) within the ratings. recommended operating conditions parameter symbol conditions min. typ. max. unit supply voltage v dd3 3.0 3.3 3.6 v v dd5 note +3.3 v pci 3.0 3.3 3.6 v v dd5 note +5 v pci 4.75 5.00 5.25 v operating ambient temperature t a 0 +70 c high-level input voltage v ih1 input pins except pci 2.0 5.5 v v ih2 rst_b pin 2.2 v dd5 + 0.5 v v ih3 pci pins except rst_b 2.0 v dd5 + 0.5 v low-level input voltage v il1 input pins except pci 0 +0.8 v v il2 pci pin - 0.5 +0.8 v note v dd5 : dedicated power supply for clamping diode 13 m m m m pd98409 dc charateristics (t a = 0 to +70 c, v dd3 = +3.3 v 0.3 v) parameter symbol conditions min. typ. max. unit high-level output voltage v oh1 i oh = - 2.0 ma note 1 2.4 v v oh2 i oh = - 12.0 ma note 2 2.4 v low-level output voltage v ol1 i ol = 3.0 ma note 3 0.55 v v ol2 i ol = 6.0 ma note 4 0.55 v v ol3 i ol = 6.0 ma note 5 0.40 v v ol4 i ol = 12.0 ma note 6 0.40 v supply current i dd f clk = 33 mhz, normal transmission/ reception 250 400 ma input leakage current (normal input) i i1 v i = v dd3 10 - 4 10 m a input leakage current (e2pdi pin with pull-up resistor) i i2 v i = gnd 10 80 200 m a notes 1. v oh1 applies to all output pins except pins po3-po0. 2. v oh2 applies to pins po3-po0. 3. v ol1 applies to pci output pins ad31-ad0, pcbe3_b-pcbe0_b, par, req_b and intr_b. 4. v ol2 applies to pci output pins frame_b, trdy_b, irdy_b, devsel_b, stop_b, serr_b, and perr_b. 5. v ol3 applies to pins other than pci output pins and pins other than pins po3-po0. 6. v ol4 applies to pins po3-po0. capacitance (t a = +25 c, v dd3 = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz 10 20 pf output capacitance c out f = 1 mhz 10 20 pf i/o capacitance c i/o f = 1 mhz 10 20 pf 14 m m m m pd98409 ac characteristics (t a = 0 to +70 c, v dd3 = +3.3 v 0.3 v) busclk input parameter symbol conditions min. typ. max. unit clk cycle time t cyclk 30 125 ns clk high-level width t clkh 11 ns clk low-level width t clkl 11 ns clk amplitude v ppclk 2v clk through rate slew clk 1 4 v/ns @ ? @@ ?? @@@@@@@ ??????? @@@ ??? @@@ ??? @ ? @ ? @@ ?? @ @ @ @ ? ? ? ? @@ ?? @ @ @ @ ? ? ? ? @ @ @ @ ? ? ? ? @ @ @ @ ? ? ? ? @ @ ? ? @ @ @ ? ? ? @ @ ? ? t clkh 2.0 v 1.5 v clk 0.8 v t clkl 2.4 v (min.) 0.4 v (max.) t cyclk v ppclk rst input parameter symbol conditions min. typ. max. unit rst low-level width t rstl t cyclk ns rst through rate slew rst 50 mv/ns 15 m m m m pd98409 pci bus interface bus master read parameter symbol conditions min. typ. max. unit clk -? frame_b valid time t dframe 211ns clk -? ad (address) valid time t daddr 211ns clk -? ad (address) float time t daddrf 28 ns ad (data) setup time t sdata 7ns ad (data) hold time t hdata 2 note 1 ns clk -? pcbe_b valid time t dpcbe 211ns clk -? pcbe_b float time t dpcbef 28 ns clk -? irdy_b valid time t dirdy 211ns clk -? irdy_b float time t dirdyf 28 ns trdy_b setup time t strdy 9 note 2 ns trdy_b hold time t htrdy 2 note 1 ns devsel_b setup time t sdevsel 7ns devsel_b hold time t hdevsel 2 note 1 ns clk -? par valid time t dpar 211ns clk -? par float time t dparf 28 ns par setup time t spar 7ns par hold time t hpar 2 note 1 ns clk -? perr_b valid time t dperr 211ns clk -? perr_b float time t dperrf 28 ns notes 1. relaxed specification from pci local bus specification revision 2.1 0 ns ? 2 ns 2. relaxed specification from pci local bus specification revision 2.1 7 ns ? 9 ns 16 m m m m pd98409 bus master read @@ ?? @@ ?? @ @ ? ? @ @ ? ? @ @ @ @ @ @ ? ? ? ? ? ? @ ? @ @ @ ? ? ? @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? @ ? @ @ @ @ @ @ ? ? ? ? ? ? @ @ @ @ @ @ @ ? ? ? ? ? ? ? @@ ?? @ ? @ @ @ ? ? ? @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? @ ? @ @ @ @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? ? ? ? @ @ ? ? @ @ ? ? @ @ ? ? @ @ ? ? @ @ ? ? @ ? @ @ ? ? @@ ?? @ @ @ @ @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? ? ? ? ? @@ ?? @ @ ? ? @@ ?? @ @ ? ? @ @ ? ? @ @ ? ? @@ ?? @@ ?? @ ? @@ ?? @ ? @@ ?? @ ? @ ? @@ ?? @@ ?? @@ ?? @ ? @ @ ? ? @ ? @ @ ? ? @ @ ? ? @ ? @ @ ? ? @ ? @ ? @ @ ? ? @@ ?? t dframe t daddr t dpcbe t dirdy t dirdyf t htrdy t strdy t hdevsel t sdevsel t dparf t dpar t hpar t spar t dperr t dperrf (input) (output) (address) (data) t daddrf t sdata t hdata t dpcbef clk frame_b ad31-ad0 pcbe3_b- pcbe0_b irdy_b trdy_b devsel_b par perr_b 17 m m m m pd98409 bus master write parameter symbol conditions min. typ. max. unit clk - ? frame_b valid time t dframe 211ns clk - ? ad (address) valid time t daddr 211ns clk - ? data valid time t ddata 211ns clk - ? data float time t ddataf 28 ns clk - ? pcbe_b valid time t dpcbe 211ns clk - ? pcbe_b float time t dpcbef 28 ns clk - ? irdy_b valid time t dirdy 211ns clk - ? irdy_b float time t dirdyf 28 ns trdy_b setup time t strdy 9 note 2 ns trdy_b hold time t htrdy 2 note 1 ns devsel_b setup time t sdevsel 7ns devsel_b hold time t hdevsel 2 note 1 ns clk - ? par valid time t dpar 211ns clk - ? par float time t dparf 28 ns perr_b setup time t sperr 7ns perr_b hold time t hperr 2 note 1 ns notes 1. relaxed specification from pci local bus specification revision 2.1 0 ns ? 2 ns 2. relaxed specification from pci local bus specification revision 2.1 7 ns ? 9 ns 18 m m m m pd98409 bus master write @@ ?? @@ ?? @ @ ? ? @ @ ? ? @ @ @ @ @ @ ? ? ? ? ? ? @@ ?? @ @ @ ? ? ? @ @ @ @ @ @ ? ? ? ? ? ? @ ? @ ? @ @ @ ? ? ? @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? @@ ?? @ @ @ @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? ? ? ? @ @ ? ? @ ? @ @ ? ? @ ? @ @ @ @ @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? ? ? ? ? @@ ?? @ @ ? ? @@ ?? @ @ ? ? @@ ?? @ ? @@ ?? @@ ?? @ ? @@ ?? @@ ?? @ @ ? ? @ ? @ ? @ @ ? ? @ @ ? ? @@ ?? @ ? @ ? @ ? @ @ ? ? @@ ?? t dframe t daddr t dirdy @ ? @@ ?? t dpar t dirdyf t htrdy t strdy t hdevsel t sdevsel t dparf t sperr t hperr (output) (output) (address) (data) t d data t dpcbe t d data f @@ ?? t dpcbef clk frame_b ad31-ad0 pcbe3_b- pcbe0_b irdy_b trdy_b devsel_b pa r perr_b @ ? @ @ @ @ ? ? ? ? @ @ @ @ @ @ @ ? ? ? ? ? ? ? @ @ @ @ @ @ ? ? ? ? ? ? @@ ?? @ ? @ ? 19 m m m m pd98409 target read parameter symbol conditions min. typ. max. unit frame_b setup time t sframe 7ns frame_b hold time t hframe 2 note 1 ns ad (address) setup time t saddr 7ns ad (address) hold time t haddr 2 note 1 ns clk - ? ad (data) valid time t ddata 211ns clk - ? ad (data) float time t ddataf 28 ns pcbe_b setup time t spcbe 7ns pcbe_b hold time t hpcbe 2 note 1 ns irdy_b setup time t sirdy 9 note 2 ns irdy_b hold time t hirdy 2 note 1 ns clk - ? trdy_b valid time t dtrdy 211ns clk - ? trdy_b float time t dtrdyf 28 ns clk - ? devsel_b valid time t ddevsel 211ns clk - ? devsel_b float time t ddevself 28 ns par setup time t spar 7ns par hold time t hpar 2 note 1 ns clk - ? par valid time t dpar 211ns clk - ? par float time t dparf 28 ns perr_b setup time t sperr 7ns perr_b hold time t hperr 2 note 1 notes 1. relaxed specification from pci local bus specification revision 2.1 0 ns ? 2 ns 2. relaxed specification from pci local bus specification revision 2.1 7 ns ? 9 ns 20 m m m m pd98409 target read @ ? @ @ ? ? @ @ ? ? @ ? @@ ?? @ @ @ ? ? ? @ ? @ @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? ? @ @ ? ? @@ ?? @ ? @ @ @ ? ? ? @ @ @ @ @ @ ? ? ? ? ? ? @ ? @ @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? ? @ @ ? ? @ ? @ @ ? ? @ ? @ @ @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? ? ? @ ? @ ? @ ? @ ? @ ? @ ? @ @ ? ? @ ? @ @ ? ? @ @ ? ? @@ ?? @ ? @@ ?? @@@ ??? @@ ?? @ ? @ @ ? ? @@ ?? @ @ ? ? @ ? @ @ ? ? @ ? @ ? @ @ ? ? @@ ?? t sframe t saddr t haddr t hframe @ @ ? ? @ @ ? ? @@ ?? t hpar t spar t dtrdyf @ @ ? ? @@ ?? t ddevself t dtrdy t sirdy t hirdy t dpar t ddevsel t dparf t sperr t hperr (output) (input) (address) (data) t d data t spcbe t hpcbe t d data f clk frame_b ad31-ad0 pcbe3_b- pcbe0_b irdy_b trdy_b devsel_b pa r perr_b @ @ ? ? @ @ ? ? @@ ?? @@ ?? 21 m m m m pd98409 target write parameter symbol conditions min. typ. max. unit frame_b setup time t sframe 7ns frame_b hold time t hframe 2 note 1 ns ad (address) setup time t saddr 7ns ad (address) hold time t haddr 2 note 1 ns ad (data) setup time t sdata 7ns ad (data) hold time t hdata 2 note 1 ns pcbe_b setup time t spcbe 7ns pcbe_b hold time t hpcbe 2 note 1 ns irdy_b setup time t sirdy 9 note 2 ns irdy_b hold time t hirdy 2 note 1 ns clk - ? trdy_b valid time t dtrdy 211ns clk - ? trdy_b float time t dtrdyf 28 ns clk - ? devsel_b valid time t ddevsel 211ns clk - ? devsel_b float time t ddevself 28 ns par setup time t spar 7ns par hold time t hpar 2 note 1 ns clk - ? perr_b valid time t dperr 211ns clk - ? perr_b float time t dperrf 28 ns notes 1. relaxed specification from pci local bus specification revision 2.1 0 ns ? 2 ns 2. relaxed specification from pci local bus specification revision 2.1 7 ns ? 9 ns 22 m m m m pd98409 target write @ ? @ @ ? ? @ @ ? ? @ ? @@ ?? @ @ @ ? ? ? @ ? @ @ @ ? ? ? @ @ ? ? @ @ @ @ @ ? ? ? ? ? @ ? @@ ?? @ ? @ @ @ ? ? ? @ @ @ @ @ @ ? ? ? ? ? ? @ ? @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? @ ? @ @ ? ? @ ? @ @ @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? ? ? @ ? @@ ?? @ ? @ ? @ ? @ ? @ ? @ @ ? ? @ @ ? ? @ @ ? ? @ @ ? ? @@ ?? @ ? @@ ?? @@ ?? @ ? @ @ ? ? @ ? @ @ ? ? @ ? @ @ ? ? t sframe t saddr t haddr t hframe @ @ ? ? @ @ ? ? @ @ ? ? @@ ?? t hpar t spar t dtrdyf @ ? @@ ?? t ddevself t dtrdy t sirdy t hirdy t ddevsel t dperr t dperrf (input) (input) (address) (data) t s data t spcbe t hpcbe t h data clk frame_b ad31-ad0 pcbe3_b- pcbe0_b irdy_b trdy_b devsel_b pa r perr_b @ @ ? ? @ @ ? ? @@ ?? @@ ?? 23 m m m m pd98409 bus arbitration parameter symbol conditions min. typ. max. unit clk - ? req_b valid time t dreq 212ns gnt_b setup time t sgnt 10 ns gnt_b hold time t hgnt 2 note ns note relaxed specification from pci local bus specification revision 2.1 0 ns ? 2 ns bus arbitration @ @ ? ? @ ? @ ? @@ ?? @ @ @ ? ? ? @@ ?? @ ? @ @ ? ? @ ? @ @ ? ? @ @ ? ? @@ ?? t dreq t sgnt t hgnt clk req_b gnt_b 24 m m m m pd98409 configuration read parameter symbol conditions min. typ. max. unit frame_b setup time t sframe 7ns frame_b hold time t hframe 2 note 1 ns ad (address) setup time t saddr 7ns ad (address) hold time t haddr 2 note 1 ns clk - ? ad (data) valid time t ddata 211ns clk - ? ad (data) float time t ddataf 28 ns pcbe_b setup time t spcbe 7ns pcbe_b hold time t hpcbe 2 note 1 ns idsel setup time t sidsel 7ns idsel hold time t hidsel 2 note 1 ns irdy_b setup time t sirdy 9 note 2 ns irdy_b hold time t hirdy 2 note 1 ns clk - ? trdy_b valid time t dtrdy 211ns clk - ? trdy_b float time t dtrdyf 28 ns clk - ? devsel_b valid time t ddevsel 211ns clk - ? devsel_b float time t ddevself 28 ns clk - ? par valid time t dpar 211ns clk - ? par float time t dparf 28 ns par setup time t spar 7ns par hold time t hpar 2 note 1 ns perr_b setup time t sperr 7ns perr_b hold time t hperr 2 note 1 ns notes 1. relaxed specification from pci local bus specification revision 2.1 0 ns ? 2 ns 2. relaxed specification from pci local bus specification revision 2.1 7 ns ? 9 ns 25 m m m m pd98409 configuration read @ @ ? ? @ @ ? ? @ ? @ ? @ ? @ ? @ @ @ ? ? ? @ ? @@ ?? @ ? @ @ @ ? ? ? @ @ @ @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? ? ? ? @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? @@ ?? @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ @@ ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? @@ ?? @@ ?? @@ ?? @@ ?? @ ? @ @ ? ? @ @ ? ? @ @ ? ? @ @ ? ? @ @ ? ? @ ? @ @ ? ? @ @ ? ? @ @ ? ? @ @ ? ? @ @ @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? ? ? @ @ ? ? @@ ?? @@ ?? @@ ?? @@ ?? @@ ?? @ @ ? ? @ ? @ @ ? ? @ ? @ @ ? ? @@ ?? @ ? t sframe t saddr t spcbe t haddr t hpcbe @@ ?? t sidsel t hidsel t hframe t sirdy t hirdy @@@ ??? @ ? @ ? t spar t hpar t ddevsel t dtrdy t sperr t dtrdyf @@ ?? @ @ ? ? t ddevself @@ ?? t dparf t dpar t hperr (output) (input) (address) (data) t d data t d data f clk frame_b ad31-ad0 pcbe3_b- pcbe0_b idsel irdy_b trdy_b devsel_b pa r perr_b @ ? @ ? @ @ ? ? @ @ ? ? @ ? @ @ ? ? @ @ ? ? @ ? 26 m m m m pd98409 eeprom interface parameter symbol conditions min. typ. max. unit e2pclk high-level width t we2pclkh t cyclk 18 - 50 t cyclk 18 t cyclk 18 + 50 ns e2pclk low-level width t we2pclkl t cyclk 18 - 50 t cyclk 18 t cyclk 18 + 50 ns e2pclk ? e2pcs valid time t de2pcs 50 ns e2pcs - ? e2pclk t se2pcs 50 ns p2pclk ? e2pdo valid time t de2pdo 300 ns e2pdi ? e2pclk setup time t se2pdi 500 ns e2pclk ? e2pdi hold time t he2pdi 70 ns e2pcs - ? e2pdi (status) valid delay time t de2pstv 500 ns e2pcs ? e2pdi (status) invalid delay time t de2psti 0 100 ns eeprom interface @ @ ? ? @ ? @ ? @ ? @ ? @ @ @ ? ? ? @ ? @ @ @ ? ? ? @ ? @ @ ? ? @ @ @ @ @ ? ? ? ? ? @@ ?? @ ? @@ ?? @@ ?? @@ ?? @ ? @@ ?? @@@@ ???? @@@@ ???? @@ ?? @ @ ? ? t de2pcs t de2pdo t se2pcs t we2pclkh t we2pclkl t de2pcs t se2pdi t he2pdi (status) t de2psti t de2pstv e2pcs e2pclk e2pdo e2pdi (read) e2pdi (status) @ @ @ @ @ @ ? ? ? ? ? ? @ ? @ @ @ @ @ @ ? ? ? ? ? ? @ @ @ @ ? ? ? ? @ @ ? ? @ @ ? ? @ @ ? ? 27 m m m m pd98409 utopia interface transmission operation parameter symbol conditions min. typ. max. unit tclk - ? tx delay time t dtx 318ns tclk - ? tsoc delay time t dtsoc 318ns tclk - ? tenbl_b delay time t dten 318ns full_b setup time t sfull 8ns full_b hold time t hfull 1ns reception operation parameter symbol conditions min. typ. max. unit rx setup time t srx 8ns rx hold time t hrx 1ns rsoc setup time t srsoc 8ns rsoc hold time t hrsoc 1ns rclk - ? renbl_b delay time t dren 318ns empty_b setup time t sempt 8ns empty_b hold time t hempt 1ns 28 m m m m pd98409 @@@@@@@@ ???????? @@ ?? @ @ @ @ ? ? ? ? t dtsoc t dtx t dtsoc t sfull h1-h4: atm header p1-p9: payload data t hfull t dten p9 p8 p7 p6 p5 p4 p3 invalid p2 p1 ?0h h4 h3 h2 tclk tx7-tx0 tsoc tenbl_b utopia interface (1) transmission operation full_b h1 @ ? @@ ?? @@@ ??? @ @ ? ? @ ? @ @ ? ? t dten @ @ ? ? @ @ @ ? ? ? @ ? @@@ ??? @ @ ? ? @ ? @@@ ??? @@@ ??? @ ? @@@ ??? @ @ @ ? ? ? @@@@@ ????? @@@@@@ ?????? @@@@@ ????? @@@@@@ ?????? 29 m m m m pd98409 @@@@@@ ?????? @@@@@@@@ ???????? @@@@@@@@ ???????? @@ ?? @ @ @ @ ? ? ? ? t srsoc t srx t hrx t hrsoc t sempt h1-h4: atm header p1-p7: payload data t hempt t dren t dren p7 p6 p5 p4 p3 invalid p2 p1 h5 h4 invalid h3 h2 rclk rx7-rx0 rsoc renbl_b utopia interface (2) reception operation empty_b h1 @ ? @@ ?? @@ ?? @ @ ? ? @ @ ? ? @ ? @ @ ? ? @ @ ? ? @ @ ? ? @ @ ? ? @ ? @ ? @@@ ??? @ @ ? ? @@ ?? @@ ?? @ ? @@@ ??? @@@ ??? @ @ @ ? ? ? @@@@@ ????? @@@@@@ ?????? 30 m m m m pd98409 phy status access write parameter symbol conditions min. typ. max. unit clk - ? ca delay time t dpca 20 ns clk - ? phrw_b delay time t dphrw 20 ns clk - ? phce_b delay time t dphce 20 ns clk - ? cd delay time t dpcd 20 ns phce_b - ? cd float time t fpcd 1t cyclk - 10 1t cyclk + 10 ns write timing @ @ @ ? ? ? @ @ @ ? ? ? @ ? @@ ?? @ ? @@@ ??? @@ ?? @ ? @ @ ? ? @ @ ? ? @ @ ? ? @ @ @ @ @ @ ? ? ? ? ? ? @@ ?? t fpcd t dphce @@ ?? @ @ ? ? @ ? @@ ?? @ @ ? ? @@ ?? @@ ?? @@@@@@@ ??????? t dphce t dpcd ?h? t dphrw @@ ?? t dpca 1 clock 4 clocks 1 clock t dpca t dphrw @ @ @ @ ? ? ? ? @ @ ? ? @ @ ? ? @ ? @ ? @ @ @ @ ? ? ? ? @ ? @ ? @ ? @ ? @@ ?? (output) clk ca8-ca0 phrw_b phce_b phoe_b cd7-cd0 read parameter symbol conditions min. typ. max. unit cd setup time t spcd 0ns cd hold time t hpoecd 0ns clk - ? ca delay time t dpca 20 ns clk - ? phrw_b delay time t dphrw 20 ns clk - ? phce_b delay time t dphce 20 ns clk - ? phoe_b delay time t dphoe 20 ns 31 m m m m pd98409 @@@@@@ ?????? @@@@@@@@ ???????? @@ ?? @@@ ??? @@ ?? @ @ ? ? @ @ ? ? @@ ?? @ ? @@ ?? @@ ?? @ @ ? ? @ @ ? ? @ @ ? ? @@@@ ???? t dphce @ @ @ @ ? ? ? ? @ ? @ ? t dphoe t dphoe t spcd t hpoecd @ @ ? ? @ @ ? ? @@ ?? @ @ ? ? @@ ?? @ @ ? ? @ @ ? ? @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t dphce @ @ ? ? t dpca 1 clock 6 clocks 5 clocks 4 clocks t dpca t dphrw @@ ?? @ ? @ ? @ ? @@ ?? @ ? @@@ ??? (input) clk ca8-ca0 phrw_b read timing phce_b phoe_b cd7-cd0 32 m m m m pd98409 others parameter symbol conditions min. typ. max. unit phint_b setup time t sphi 8ns phint_b hold time t hphi 1ns clk - ? po delay time t dpo 225ns clk - ? rstout_b delay time t drsto 225ns rstout_b output pulse width t wrsto 11 22 t cyclk other timing @ @ ? ? @ @ ? ? @ @ ? ? @@ ?? @ ? @ @ ? ? @ ? t hphi @@ ?? t dpo @@@@@@@@@@@ ??????????? t wrsto t sphi t drsto @ @ @ @ @ ? ? ? ? ? clk phint_b po3-po0 rstout_b @ ? @ @ ? ? @ ? @ @ ? ? @ ? 33 m m m m pd98409 3. package drawing 240 pin plastic qfp (fine pitch) (32x32) item millimeters inches p240gn-50-lmu, mmu-2 a b c 32.0?.2 32.0?.2 34.6?.2 1.362?.008 1.260?.008 1.260?.008 d f 34.6?.2 1.25 1.362?.008 0.049 g 1.25 0.049 i j 0.10 0.5 (t.p.) 0.004 0.020 (t.p.) l 0.5?.2 0.020 +0.009 ?.008 p 3.2?.1 0.126?.004 n 0.10 0.004 q 0.4?.1 0.016 +0.004 ?.005 s 3.8 max. 0.150 max. r3 +7 ? 3 +7 ? h 0.22 0.009?.002 +0.05 ?.04 m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 n detail of lead end i j f g h q r p k m l m s note 1. controlling dimention millimeter. 2. each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. 180 121 120 181 61 240 160 s a b cd s k 1.3?.2 0.051 +0.009 ?.008 34 m m m m pd98409 4. soldering conditions solder the product under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e). for soldering methods and soldering conditions other than those recommended, consult nec. surface mount type m pd98409gn-lmu: 240-pin plastic qfp (0.5-mm fine pitch) (32 32 mm) soldering method soldering conditions symbol of recommended condition infrared reflow package peak temperature: 235 c, time: 30 seconds max. (210 c min.), number of times: once, number of days: 3 note (afterwards, prebaking is necessary at 125 c for 20 hours.) 35 m m m m pd98409 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function. m m m m pd98409 neascot-s40c and eeprom are trademarks of nec corporation. microwire is a trademark of national semiconductor corporation. the export of this product from japan is prohibited without governmental license. to export or re-export this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5 |
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